1. Field of the Invention
Embodiments of the invention relate to power amplifiers and more particularly to reconfiguration of power amplifiers for operation in different power modes.
2. Description of the Related Art
FIG. 1a shows an example of a radio frequency (RF) power amplifier (PA) known in the art. The RF PA shown in FIG. 1a has a gain stage, 11, followed by a matching network 13. Output node 10 is coupled to the load, symbolically presented as resistor 7, typically 50 ohms. The matching network 13 plays the role of an impedance transformation network, which converts the relatively high load impedance (e.g. 50 Ohms) into a lower impedance (e.g. 5 ohms) as seen by the output 8 of the final PA stage 11. The lower impedance reduces the maximum voltage swing present at node 8 necessary for injecting the needed maximum output power into the load 7. The matching network exemplified in FIG. 1 consists of the inductor 4 and capacitor 5, which, together with load inductor 3, form a tuned transformation circuit. Capacitor 6 blocks the DC voltage present at node 9 from reaching the load 7. The RF amplifier stage 11 receives its input on node 1.
The RF PA stage 11 consists of active device, MOSFET 2, connected in a common-source configuration, and inductor 3, connected between node 8 and power supply Vdd. The current through transistor 2 is controlled by the voltage difference between the gate terminal, connected to input node 1, and the source terminal, connected to ground. The drain of transistor 2 is connected to node 8. The voltage signal at node 8 is substantially in phase opposition to the voltage signal on the gate node 1 as a direct consequence of the common-source configuration of transistor 2. Inductor 3 plays two roles: it supplies the DC power to the active device 2 and it completes the resonant transformation network in conjunction with block 13.
The operation of the PA presented in FIG. 1a is qualitatively illustrated by the waveforms in FIG. 1b. The PA stage 11 receives on node 1 the sinusoidal voltage waveform shown in the top graph. As a result, the current traversing the active element MOSFET 2 from drain to source will present a waveform substantially in phase to the waveform on node 1, exemplified in the middle graph of FIG. 1b. The voltage on node 8 will present a waveform substantially in phase opposition to the waveform on node 1, exemplified in the bottom graph of FIG. 1b. 
The electrical power absorbed from the power supply connected to Vdd is dissipated in only two devices shown in FIG. 1a: load resistor 7 and MOSFET 2. The power dissipated in load resistor 7 represents the useful generated power that the RF PA produces and is the sole purpose of the PA. The power dissipated on the active device 2 is generally wasted as heat and brings no benefits to the PA. Thus, the efficiency of the PA, defined as the ratio of useful power to the total power absorbed from the supply, is greater if the amount of power dissipated on the active device 2 is smaller.
The PA of FIG. 1a can generate an arbitrary output RF power up to a maximum output power by means of controlling the amplitude of the voltage waveform at the input node 1. When the voltage on input node 1 changes, the amplitude of PA output 8 changes and power generated in PA load 7 changes. Maximum output power is limited by the maximum voltage amplitude achievable at node 8.
The graph presented in FIG. 2, curve 1 shows the typical relationship between the PA efficiency and the output power generated by the PA. This relationship is described as the smaller the output power, the lower the efficiency and is further explained below.
With respect to FIG. 1a, the average voltage between the drain and the source of the MOSFET 2 is always constant and equal to VDD. The RF voltage swing across the device periodically reduces and enhances the drain to source voltage. Due to the substantial phase opposition between the current waveform traversing MOSFET 2 from drain to source and the voltage waveform between the drain and source, the power dissipated as heat by MOSFET 2 is greater when the amplitude of the voltage waveform between the drain node 8 and the ground node is smaller. When the input of the PA stage is driven such that it generates a smaller output power, the amplitude of the voltage waveform at node 8 is smaller, increasing the power dissipated by the MOSFET 2. Thus, the smaller the output power, the lower the efficiency.
A PA that supports operation on two different power curves such as those shown in FIG. 2 is said to be operating in high power mode when on curve 1 and is said to be operating in low power mode when on curve 2. Some PAs may also offer more than 2 power modes. For example a PA that provides 3 power curves is said to operate in high, mid, and low power modes depending on which curve it is on. For simplicity the following discussion assumes only two power modes are present. However, it should be understood that the embodiments described below could be modified to add additional power modes.
FIG. 3a shows an embodiment of a PA stage of the prior art. It comprises gain stage 15 and transformation network 16. Resistor 10, connected between node 14 and ground, is the single-ended PA load. Gain stage 15 comprises a pair of complementary MOSFET devices, pFET 3 and nFET 4. The complementary MOS devices 3 and 4 are employed in common-source configuration, where their sources are connected to two power supply nodes, Vdd and ground, respectively, while their drains are connected to nodes 11 and 12, respectively. Inductor 5 connects node 11 and node 12 together and has two functions: allows for the flow of DC current between the two complementary devices and resonates with the capacitive component of the load impedance presented by the transformation network 16 and with parasitics to power and ground on nodes 11 and 12. The gates 1 and 2 of the complementary devices 3 and 4 are the inputs of the gain stage. Even though the PA in FIG. 3a resembles a push-pull amplifier topologically, it is fundamentally different in that the inputs 1 and 2 are driven by signals with waveform in phase opposition, as shown in the bottom graph of FIG. 3b. It is said that the inputs 1 and 2 of the gain stage form a differential node pair. The output nodes of the gain stage, 11 and 12, present voltage waveforms that are also substantially in phase opposition, as depicted in the top graph of FIG. 3b. Nodes 11 and 12 also form a differential node pair.
The gain stage 15 can operate either in nonlinear or linear modes. In nonlinear operation the inputs 1 and 2 are driven hard and the outputs 11 and 12 have voltage swings that are independent of the input amplitude. In linear operation the inputs 1 and 2 are driven with small signals and the outputs 11 and 12 have voltage swings that are proportional to their inputs. In the event that the PA is in linear operation a smaller output power is the result of smaller swings at nodes 11 and 12. Maximum output power is limited by the maximum differential voltage amplitude achievable at differential nodes 11 and 12. The gain stage described above will be, hereafter, referred to as the Class P amplifier stage.
The prior art transformation network 16 of FIG. 3a comprises the impedance elements inductor 6 and capacitors 7, 8, and 9. The values of inductor 6 and capacitor 7 can be chosen to transform the value of the PA single-ended load resistance, 10, (e.g. 50 Ohm) into a desired differential impedance between nodes 11 and 12 (e.g. 5 Ohms). Inductor 6 and capacitor 7 in the configuration of FIG. 3a, simultaneously perform the functions of impedance transformation and differential-to-single-ended conversion. Capacitor 8 controls the reactive nature of the impedance seen by the gain stage at node 11 as it is presented by the transformation network. Capacitor 9 is employed as a DC blocking element and can be chosen to have a very large value so as to not significantly influence the behavior of the transformation network.
In a manner substantially analogous to the behavior of the PA gain stage 11 of FIG. 1a, the gain stage 15 of FIG. 3a presents drain node voltages, differential nodes 11 and 12, exhibiting a substantially constant DC voltage irrespective of the output power generated by the PA. The relationship between efficiency and output power for the amplifier of FIG. 3a is also characterized by curve 1 of FIG. 2.